1. Field of the Invention
The present invention relates to a design method of a semiconductor integrated circuit, particularly for an automatic design method of wiring of a semiconductor integrated circuit.
2. Description of the Related Art
As a space between wires is reduced along with the miniaturization of a semiconductor integrated circuit, crosstalk attributable to coupling capacitance between the wires has a significant influence on characteristics of the semiconductor integrated circuit. The influence of crosstalk between the wires includes crosstalk noise, crosstalk delay, and the like. The “crosstalk noise” is a phenomenon when a change of a signal transmitted on an affecting wire causes a voltage change in an adjacent wire. The wire affected by the crosstalk will be hereinafter referred to as a “victim wire”, and the affecting wire will be hereinafter referred to as an “aggressor wire”. The crosstalk noise has a risk of causing malfunction in the semiconductor integrated circuit. In the meantime, the “crosstalk delay” is a phenomenon, when signal arrival time of the aggressor wire overlaps signal arrival time of the victim wire, so that the victim wire on which transition of a signal starts earlier is affected by the transition of a signal on the aggressor wire and a delay in transmission time of the signal on the victim wire is thereby caused. The crosstalk delay causes malfunction or characteristic deterioration of the semiconductor integrated circuit.
In general, a method of wiring a semiconductor integrated circuit is started by dividing a wiring region of a semiconductor integrated circuit after determination of a layout of circuit elements into a plurality of global routing grids. Then, global wiring is carried out for determining which global routing grid the wire passes through. The wire passing through the global routing grid is called “global wire”. Thereafter, detail wiring is carried out for determining a layout of wires inside each of the global routing grids. To reduce the influence of the crosstalk, Japanese Patent Laid Open Publication No. 2000-223578 discloses a wiring method in which the influence of the crosstalk is evaluated by carrying out tentative detail wiring after the global wiring, then a crosspoint where the wire intersects with a boundary of the global routing grid is set up based on a result of the evaluation, and then the global wiring is carried out again. Alternatively, there is disclosed a method of improving the influence of the crosstalk by evaluating a possibility of a crosstalk delay after carrying out the global wiring, and by setting up a crosspoint where the wire intersects with a boundary of the global routing grid before the detail wiring (H.-P. Tseng et al., IEEE Trans. Computer-Aided Design, vol. 20, No. 4, p. 528 (2001)).
However, according to the wiring method disclosed in Japanese Patent Laid Open Publication No. 2000-223578, the detail wiring has severe restrictions because all the positions on the boundaries where the wires intersect with the global routing grids are set up before the detail wiring. Moreover, although it is necessary to widen the space between wires to reduce capacitances between the wires, the space between wires cannot be sufficiently widened in a region where wiring density is high. In this case, it is difficult to reduce the crosstalk.
Meanwhile, according to the method disclosed by H.-P. Tseng et al, all the positions on the boundaries where all the wires intersect with the global routing grids are determined before the detail wiring. Therefore, the detail wiring has severe restrictions and has difficulty when the wiring density inside the global routing grids is high. Moreover, since the influence of the crosstalk is taken into account by converting it into delay time, it is not possible to evaluate the influence of the crosstalk noise. Furthermore, it is not possible to optimize the wiring in consideration of overlaps of signal arrival time from among a plurality of the aggressor wires.